The present invention relates to a semiconductor device design and a test technique, and more particularly, to a semiconductor device and an interface board for testing the semiconductor device to improve a test efficiency.
A semiconductor device is fabricated through design, process and test steps. It is important to reduce the fabrication time and costs in performing the manufacturing steps.
Recently, as semiconductor devices are desired to have high speed and high integrated characteristics, the fabrication time and processing costs are increased in the design and process steps. Particularly, it is desired to perform various tests because the semiconductor device may have an internal error.
FIG. 1 is a block diagram for illustrating a conventional test circuit for a semiconductor device.
Referring to FIG. 1, the conventional test circuit for the semiconductor device includes a plurality of semiconductor devices 11 to 14 and a test device 10.
The semiconductor devices 11 to 14 are coupled to the test device through a plurality of voltage channels. The semiconductor devices 11 to 14 are allocated to first to fourth channels of the test device 10. N number of voltages are transferred through one voltage channel, where N denotes an integer.
The test device 10 applies a plurality of test voltages to the semiconductor devices 11 to 14 through a respective voltage channel, and probes a plurality of internal voltages outputted from the semiconductor device through the identical voltage channel.
That is, while forcing a plurality of identical tests to a plurality of semiconductor devices 11 to 14, the identical test voltages are transferred through a voltage channel allocated to each of the semiconductor devices 11 to 14. In forcing a plurality of identical tests, a test device detects an error by applying an identical voltage to a semiconductor device. While a plurality of internal voltages outputted from each of the semiconductor devices 11 to 14 are probed, the internal voltages are transferred to each of the semiconductor devices 11 to 14 through the voltage channel allocated to the respective one of the semiconductor devices 11 to 14.
Accordingly, because the voltage channel should be allocated to each of the semiconductor devices and one voltage channel has N voltage transferring interfaces, a large number of voltage transferring interfaces, e.g., channels, are desired to test the semiconductor devices.
FIG. 2 is a block diagram illustrating a conventional semiconductor device.
Referring to FIG. 2, the conventional semiconductor device 21 transfers a plurality of internal voltages V_1 to V_N, which are generated from a plurality of internal voltage generation blocks, externally through a plurality of power pads 20_1 to 20_N, or inputs a plurality of test voltages V_TEST1 to V_TESTN, which are applied through the power pads 20_1 to 20_N, to the internal voltage generation blocks.
That is, because the power pads 20_1 to 20_N are each coupled to a voltage channel of a test device, test processes for measuring the internal voltages of the semiconductor device and for forcing test voltages to the internal voltage generation blocks may be performed through the power pads 20_1 to 20_N.
As described above, a voltage channel should be allocated to each of the semiconductor devices to test the conventional semiconductor devices at the same time.
In general, a test device performs various tests by supplying a power supply and exchanging signals after accessing a plurality of channels, e.g., a power channel, a command channel, a data channel and an address channel, through a pad of the semiconductor devices to be tested.
Accordingly, when the test device tests the conventional semiconductor devices, the number of semiconductor devices, which are tested at the same time, is limited. This increases test time and costs and an improved technology is desired to resolve this problem.